Cross-coupled MOS inverter cells, driven by capacitively-coupled complementary clock signals are efficient building blocks in charge-pumps. These cells may be used to elevate an input DC voltage to a higher voltage output level. The cells may also be used to reduce an input DC voltage to a lower voltage output level. A positive input DC voltage may optionally be reduced to an output level below zero volts.
Known applications of these cells are proposed in P. Favrat, P. Deval, M. J. Declercq, “A High-Efficiency CMOS Voltage Doubler,” IEEE Journal of Solid-State Circuits, Vol. 33, No. 3, March 1998, and R. Pelliconi et al., “Power Efficient Charge Pump in Deep Submicron Standard CMOS Technology,” Proc. 27 ESSCIRC, 2001. As illustrated in FIG. 1, which is an alternative illustration of Pelliconi's FIG. 1 or portions of FIG. 2 of J. Cha, “Analysis and Design Techniques of CMOS Charge-Pump-Based Radio-Frequency Antenna-Switch Controllers, IEEE Trans. On Circuits and Systems—I: Regular Papers, Vol. 56, No. 5, May 2009, these disclosures describe a dual-bucket cell that may act as a voltage doubler.
As illustrated in FIG. 1, herein, an input voltage Vlow is input to two MOSFET inverters. The first inverter comprises NMOS transistor M1 and PMOS transistor M3, while the second inverter comprises NMOS transistor M2 and PMOS transistor M4. Both inverters' outputs are coupled to output voltage Vhigh. A clock signal clk is coupled via capacitor C1 to the gates of M1 and M3, and the drains of M2 and M4. Circuitry for generating a clock signal is not illustrated herein, but many circuits for generating clock signals are well-known to those of ordinary skill in the art. The inverse of clock signal clk is represented as inverted clock signal nclk, which is low when clk is high and vice-versa. Circuitry for generating signal nclk is not illustrated, but is well-known in the art. The inverted clock signal nclk is coupled via capacitor C2 to the gates of M2 and M4 and the drains of M1 and M3. One of ordinary skill in the art will recognize the manner in which the circuitry illustrated in FIG. 1 may output a higher voltage at node Vhigh than is input at node Vlow.
A dual-bucket cell, for example of the type illustrated in FIG. 1, may be cascaded into multiple stages to obtain an output voltage that is a higher multiple of the input voltage by electrically connecting the output Vhigh of one cell to the input Vlow of a second cell. This may be repeated any number of times provided that the circuitry is capable of handling the input and output voltage levels. An exemplary arrangement of this type is described in R. Pelliconi et al., “Power Efficient Charge Pump in Deep Submicron Standard CMOS Technology,” Proc. 27 ESSCIRC, 2001.
FIG. 2 sets forth an example of cascaded dual-bucket cells that may be used for voltage elevation. As illustrated in FIG. 2, each of cells 205, 207, 210 and any number of intermediate cells represented by ellipses ( . . . ) may be cascaded. Each of cells 205, 207, 210, and any intermediate cells may be configured in the manner of the circuitry illustrated in FIG. 1. Input voltage V_LOW_IN is input into node 212, which corresponds to Vlow. Cell 205 receives the input at node 212 and outputs a higher voltage at node 206, which corresponds to Vhigh. Node 206 is coupled to the input Vlow of cell 207. Cell 207 receives the input at node 206 and outputs a higher voltage at node 208, which corresponds to Vhigh. Node 208 may be coupled to node 209 or, alternatively, to the input of an intermediate cell. Node 209 is coupled to the output voltage of the preceding cell and corresponds to Vlow for cell 210. Cell 210 receives the input at node 209 and outputs a higher voltage at node 211, which corresponds to Vhigh. Alternatively, as set forth above, any or all of the cells in the cascade may be configured to output a voltage that is lower than the input voltage. Thus, the labels V_LOW_IN and V_HIGH_OUT are representative of a typical use, but V_LOW_IN may actually be a higher voltage than V_HIGH_OUT.
A clock input signal CLK_IN is preferably provided to amplifiers 201, 202. Amplifier 201 outputs amplified clock signal clk to each of cells 205, 207, 210, and any intermediate nodes ( . . . ) via capacitors 203. Amplifier 202 outputs inverted clock signal nclk to each of cells 205, 207, 210, and any intermediate nodes ( . . . ) via capacitors 204. Capacitors 203 and 204 are not illustrated herein for intermediate nodes ( . . . ), but, if used, will be connected in the same fashion as those illustrated with respect to cells 205, 207, 210. That is, capacitor 203 for any intermediate nodes ( . . . ) will be connected between signal clk and the node. And capacitor 204 for any intermediate nodes ( . . . ) will be connected between signal nclk and the node.
Node 211 provides output voltage V_HIGH_OUT from cell 210. Node 211 is preferably coupled to ground via capacitor 213.
Cascaded cells of the type illustrated in FIG. 2 may be used to provide a much higher multiple of the input voltage than single cells of the type illustrated in FIG. 1. The cascaded circuit of FIG. 2 eliminates at least one of the drawbacks of a Dickson charge pump, in that it does not result in voltage drops across the diodes that are present in Dickson charge pumps.
In the preferred normal operation of the device of FIG. 2, the voltages at the various nodes 212, 206, 208, 209, 211 along the ladder are relatively regularly distributed between the voltage at V_LOW_IN and the voltage at V_HIGH_OUT. In addition, some small capacitors and relatively large resistance across each of the cells (for example, 205, 207, 210) may reduce ripple and irregular effects of leakage. Because of this, the local voltage difference across each cell 205, 207, 210 will not exceed the relatively low power supply of the clock drivers. If the well in which the devices are constructed is designed to withstand relatively high DC voltage, the local MOS transistors within each cell may be constructed with a gate made of a thin oxide layer. This thin oxide gate construction generally allows for more compact component size and higher efficiency for any given on-resistance of a component. As taught by M. D. Ker, S. L. Chen, C. S. Tsai, “Design of Charge Pump Circuit With Consideration of Gate-Oxide Reliability in Low-Voltage CMOS processes,” IEEE Journal of Solid-State Circuits, Vol. 41, No. 5, May 2006, this type of thin oxide gate structure is not expected to suffer gate-oxide reliability problems.
However, if node V_HIGH_OUT is connected to off-chip circuitry with an external final decoupling capacitor, it is desirable to make the structure insensitive to electrostatic discharge (“ESD”). Because the node V_HIGH_OUT is preferably a high voltage node, it is desirable to use ESD protection devices within the pad. Neither these devices nor the pad is illustrated herein, because such structures will be familiar to one of ordinary skill in the art. Yet, even with such structures, the on-chip voltage at node V_HIGH_OUT may be subjected to sharp and relatively high voltage transients. These transients may be much higher than the transients encountered in normal chip operating conditions in a chip having thin oxide devices. In such transients, the final cell 210 of the charge pump is exposed to the voltage transients and may be damaged or destroyed by the transient.
It would be desirable to reduce the amount of damage or destruction to the cells of the charge pump due to sharp and/or high voltage transients from off-chip sources.
It would also be desirable to reduce the amount of damage or destruction to other types of cells sensitive to overvoltage across cells. Accordingly, the invention described herein is not limited to applicability to cross-coupled MOS inverter cells.